Organisation: Google

Position: ASIC/SoC Design Verification Engineer

Department: software

Location: Karnataka


  • Plan the verification of complex digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
  • Create and enhance constrained-random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry leading formal tools.
  • Identify and write all types of coverage measures for stimulus and corner-cases.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Close coverage measures to identify verification holes and to show progress towards tape-out


  • BS degree in Electrical Engineering or Computer Science or equivalent practical experience.
  • Should have experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog for FPGAs, ASICs, and/or SoCs.
  • Must having Experience in verifying digital systems, such as ones that use standard IP components and interconnects, including microprocessor cores and hierarchical memory subsystems.
  • Should have Experience in creation of and usage of verification components and environments in a standard verification methodology such as VMM, OVM, or UVM.

Preferred Qualification:

  • Master’s degree in Electrical Engineering or Computer Science with 3 years of relevant experience, or PhD in Electrical Engineering or Computer Science.
  • Should have experience with image processing, computer vision, and/or machine learning applications.
  • Experience with performance verification of SoCs and SoC components.
  • Experience prototyping and debugging systems on Field Programmable Gate Array (FPGA) platforms.
  • Must have experience in verification of low power techniques.
  • Familiarity with SoC standard interfaces and memory system architecture.

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